This invention relates to semiconductor integrated circuit memory devices and more particularly to a high speed, serial access, fault tolerant, memory system which may use an MOS/LSI random access read/write memory cell array.
Semiconductor memory devices of the type made by the N-channel silicon-gate MOS process and employing one transistor dynamic cells are now perhaps the most widely used in computers and digital equipment. The volume of manufacture of such devices has resulted in a continuing reduction in cost according to "learning curve" theory, and this trend will continue as volume increases. In addition, improvements in line resolution and other factors have made possible increases in bit density during the last few years so that 64K bit devices are now in production, and 256K devices are being designed. Increased bit density has further reduced the cost per bit for this type of computer memory, and cost reductions will continue.
Ordinarily a computer of any size, whether main frame, minicomputer, or microcomputer, will have several different types of memory. These types may include cache, dynamic RAM, static RAM, EPROM, EAROM, ROM, buffer, magnetic bubble, CCD, several types of disc including fixed head and moving head disc, and magnetic tape. Generally the high speed access types are the most expensive and the lower speeds are cheapest, on a per bit basis. Other factors such as ease of programming, volatility, refresh overhead, size, power dissipation, etc., dictate choice of one type over another. One of the most common in current mainframe computers is moving head disc, which is relatively inexpensive, but the access time is slow. Fixed head disc has thus been used as a speed buffer between moving head disc and RAM, at a cost less than RAM but somewhat more than moving head disc.
Different manufacturing methods and equipment, different design efforts for product improvement, and different technology bases have caused the various types of computer memory to fail to take maximum advantage of the economics of scale. For example, one niche is the realm of memory is occupied by CCD's which are serial semiconductor devices adapted to the task of going from moving head disc to RAM, replacing fixed head disc. In spite of the fact that CCD's are basically similar to N-channel MOS RAM's, the vast design and manufacturing expertise available for the mainstream memory products shared by major semiconductor manufacturers has not been applicable to CCD's because of the different technologies. Thus, this memory product has not kept pace in the areas of manufacturing volume, cost reduction, and bit density increases. For this reason, computer equipment manufacturers have made use of standard dynamic RAM devices to simulate operation of CCD's to accomplish the function of buffering between moving head disc and RAM. This is somewhat cheaper, but the unused speed of dynamic RAM's results in unnecessary costs. These considerations resulted in the serial access memory device of pending applications Ser. No. 097,104 now abandoned, and Ser. No. 096,957, filed herewith now U.S. Pat. No. 4,281,401 and assigned to Texas Instruments.
An evaluation of the usage of various memory types by a CPU in typical computing systems shows that high speed RAM is not needed for direct interface with the CPU during substantial parts of commonly-used operations. Instead, high speed serial access memory is very useful in transfering blocks of data into cache or into the working registers of the CPU itself. Thus, in addition to high speed RAM, it would be desirable to have available high speed serial access memory devices which may be used as an alternative. The continuing investment in dynamic MOS RAM technology, plus the serial operation provided by the serial access RAM of applications Ser. Nos. 097,104, 097,105 and 096,957, present the capability of combining serial access with random access memory technology with substantial cost advantages.
Reduction in bar size usually results in lower cost because there are more bars per slice and also increased yield if a given probability of a defect per unit area is assumed. A significant area on the bar is needed for X and Y address decoders in a standard dynamic RAM. An addressing scheme which eliminates these decoders would be of significant aid in reducing bar size and cost.
The yield of good bars per slice in semiconductor manufacture is of continuing concern. Usually over the lifetime of manufacture of a product, the yield increases, perhaps from near zero at the beginning to over 50% when the product is mature. At the upper end of this range the product may be of low cost and quite profitable, but in the beginning low yield means high cost and high numbers of scrap bars. If some of the scrap could be salvaged, especially in the beginning of production, then substantial savings in cost and much earlier delivery of parts would result. To this end, various fault tolerant memory configurations have been devised, such as shown in U.S. Pat. No. 3,988,777 issued to Choate and assigned to Texas Instruments. Many of these, however, have been costly in bar size to implement and reduced operating speed of the memory devices.
It is the principal object of this invention to provide a high speed serial access memory system which is especially useful for implementing in semiconductor MOS/LSI devices. Another object is to provide an improved fault tolerant memory, particularly for serial access memory devices which are of lower cost and susceptible of volume production. An additional object is to provide an improved MOS/LSI memory device of high bit density at low cost.